Architecting the Executables with DEVS Unified Process ...

Who We are

Mission Dunip Tech's mission is to provide world class expertise and solutions in the areas of cross-platform netcentric modeling and simulation-based systems engineering for complex dynamical, agent-based, knowledge-based and adaptive systems; and to conduct practical and meaningful research to benefit the community at-large.
Vision We strive to bring simulation as a knowledge generating vehicle across various disciplines that advances human understanding and supports engineering of useful systems.
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Netcentric System of Systems Engineering with DEVS Unified Process

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DEVSML Studio

2016 - Integrating theory of modeling and simulation framework with MDE.png
2016 - Integrating theory of modeling and simulation framework with MDE
2016 - DEVSML Stack showing DEVS modeling language and various transformations.png
2016 - DEVSML Stack showing DEVS modeling language and various transformations
2016 - Diagram of the digital trapezoidal shaper.png
2016 - Diagram of the digital trapezoidal shaper
2016 - Performance comparison of xDEVS Coordinators.png
2016 - Performance comparison of xDEVS Coordinators
2016 - DEVSML Studio showing auto-generated DEVS Atomic visual and hierarchical representation.png
2016 - DEVSML Studio showing auto-generated DEVS Atomic visual and hierarchical representation
2016 - (a) Metamodeling layers and (b) DEVSML Studio software architecture..png
2016 - (a) Metamodeling layers and (b) DEVSML Studio software architecture.
2016 - Auto-generated Coupled model representation with port data-types.png
2016 - Auto-generated Coupled model representation with port data-types
2016 - Exponential input (left) and trapezoidal output (right) generated by the xDEVS shaper model for one single event.png
2016 - Exponential input (left) and trapezoidal output (right) generated by the xDEVS shaper model for one single event

DEVS HW-SW Co-Design

2016 - GPT DEVS structure, all implemented in software.png
2016 - GPT DEVS structure, all implemented in software
2016 - Elevator controller with the adder as a HIL component.jpg
2016 - Elevator controller with the adder as a HIL component
2016 - Elevator controller with all the four integrated circuits placed in the breadboard.jpg
2016 - Elevator controller with all the four integrated circuits placed in the breadboard
2016 - Schematic design of the circuit, drawn in a breadboard.png
2016 - Schematic design of the circuit, drawn in a breadboard
2016 - GPT DEVS structure with Processor working as a hardware device.png
2016 - GPT DEVS structure with Processor working as a hardware device